The disclosure generally relates to a memory controller and, more particularly, to the memory controller with the low density parity check code decoding capability.
In the applications involving signal communications, the error correcting code is often utilized in the receiver to correct the error in the received signal. For example, the memory controller may encode the data according to a predetermined error correcting code and write the encoded data to the memory device. When errors occur in the process of reading the encoded data, the error correcting code decoder of the memory controller may correct the error to obtain the correct data.
Although the error correcting codes may be utilized in many applications, there are still some differences when utilizing the error correcting codes in different systems. For example, in communication systems, when the condition of the communication channel is too worse for the error correcting code decoder to successfully decode, the receiver may request the transmitter to resend the same data. The transmitter may encode the data with a stronger error correcting code, re-transmit the same data in another time, and/or re-transmit the same data in another frequency so that the receiver may recover the data because of the stronger error correcting code and/or a better channel condition.
On the other hand, in the storage applications, the data are not only affected by the channel effects and the noise in the signal transmission process, but also affected by the data rot and the noise in the memory device. If the data stored in the memory device is already damaged, it is not possible to re-encode the encode data stored in the memory device with a stronger error correcting code. Besides, transmitting the damaged data in another time, another frequency, or a better channel still does not improve the condition. The approaches utilized in the communication system are apparently not applicable in the storage applications.
Moreover, for the mass produced memory devices, the quality control may often be accomplished by picking a certain samples in a huge amount of products and verifying their performance. Along with the advance in the semiconductor manufacturing technology, the dimension of the memory device keeps shrinking but the capacity of the memory device keeps increasing. Therefore, more and more errors occur when accessing the data stored in the memory devices. The error correcting code decoding capability is an essential factor for determining the quality of the memory devices. The memory controller with a stronger error correcting code decoding capability requires higher computational complexity, longer computation time, and more energy, which limits the application of the memory device. For example, the portable devices usually adopt the low power consumption memory device to extend the battery usage time. On the other hand, the memory controller usually adopts the direct memory access technique, the double pumping technique, etc. to reduce the memory access time. Therefore, the memory access time is usually far less than the error correcting code decoding time. If the error correcting code decoding time may not be reduced, the output data rate and the performance of the memory device will be severely influenced.